1. Technical Field
The present invention relates generally to semiconductor memories and more specifically to controlling of wordline signals.
2. Background Art
Microprocessors are used in many applications including personal computers and other electronic systems. A goal of any microprocessor is to process information quickly. One problem has been the communication rate between a microprocessor and main memory. The instructions to be executed by the microprocessor and the data on which operations implemented by the instructions are to be performed are stored at addresses within main memory. To access instructions and data, the microprocessor transmits addresses to main memory. The main memory decodes the address and makes the contents at the requested address available for reading and/or writing. The time required for the microprocessor to transmit an address to main memory and receive the respective contents therefrom can significantly constrain system performance.
One technique, which is used to increase the speed with which the microprocessor processes information, is to provide the microprocessor with an architecture, which includes a fast local memory called a cache memory
A cache memory is a small, fast memory that keeps copies of recently used data or instructions. When these items are reused, they can be accessed from the cache memory instead of main memory. Instead of operating at slower main memory access speeds, the microprocessor can operate at faster cache memory access speeds most of the time.
In order to further increase performance, microprocessors have come to include more than one cache memory on the same semiconductor substrate as the microprocessor.
The most commonly used cache memories use static random access memory (SRAM) circuitry, which provide high densities using wordlines and bitlines to access SRAM memory cells. However, in order to place as much memory on the microprocessor die as possible, SRAM circuitry requires minimal cell and read/write circuit architectures. To support minimal architectures, a memory cell is accessed by enabling a row wordline wire and enabling a selected column-gating transistor to read the value from the memory cell.
The use of memory circuits in battery-operated and other low-voltage devices make it desirable to operate the memory circuits at lowest voltage possible. Typically, when read or write operations are done in memory arrays, the wordline is set high with the power applied while the information stored in the memory cells is read by being transferred onto bitlines or information on the bitlines is written by being stored in the memory cells. For read operations, bitlines are then read by a sense-amplifier, or sense-amp. Sense-amps are common to all memories whether the memories are dynamic, static, Flash, or other types of memories. For write operations, information on the bitlines change the held charge in the memory cell. While the wordline is kept on, power is being consumed. The wordline remains on during and after the desired operation, whether it is a read or a write, to ensure the operation is complete; i.e., power is consumed even when no longer required.
Reading reliable results from memory circuits operating at a low-power supply voltage is complicated by the large capacitance of the wordlines and the threshold drop produced by the gating transistor. Low-power supply voltages reduce memory speed, and at very low voltages, the reliability of the information drops.
To address the reliability problem, memory circuits, which have a bootstrapped boost voltage applied to the wordlines, have been developed. The row wordline is charged to a voltage that is higher than the power supply line. In addition, the row wordline is charged prior to accessing the memory location by switching on the column-gating transistor. Boost circuits provide reliable memory operation at low voltages.
One of the problems with boost circuits is that at high voltages, the access circuitry is over-stressed. This limits the upper end of the power supply operating range of a memory device.
Another problem is that boosting increases the power consumption of a memory circuit. At high supply voltages, the power dissipation can exceed tolerable levels and the memory circuitry is subject to failures due to overheating.
Power saving has been a persistent need. Because low-power consumption is becoming even more important, it is desirable to provide a method and apparatus for operating a memory device in a manner that saves power. Furthermore, it is desirable to achieve reliable read and write operations at low voltages.
With the urgency of increasing speed and saving power, solutions to these problems have been long sought but have long eluded those skilled in the art.
The present invention provides a memory system, and method of operation therefor, having memory cells for containing data, bitlines for writing data in and reading data from the memory cells, and wordlines connected to the memory cells for causing the bitlines to write data in the memory cells in response to wordline signals. A decoder is connected to the wordlines for receiving and decoding address information in response to a clock signal and an address signal to select a wordline for a write to a memory cell. Latch circuitry is connected to the decoder and the wordlines. The latch circuitry is responsive to the clock signal for providing the wordline signal to the selected wordline for the write to the memory cell and for removing the wordline signal from the selected wordline when the write to the memory cell is complete. The memory system conserves power while permitting reliable read and write operations at low voltages.
Certain embodiments of the invention have other advantages in addition to or in place of those mentioned above. The advantages will become apparent to those skilled in the art from a reading of the following detailed description when taken with reference to the accompanying drawings.